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Sat, 09 Dec 2006
Thinking about I/O requirements
Although EMC2 is quite capable of generating step/dir signals in software, there is a limit to the maximum step rate you can generate that way. Because I want to use 10x microstepping, and I want my rapid speeds to be limited by the motors and drives, NOT by the software, I'm going to use "hardware assist". There are a number of products out there that use hardware to generate step pulses at rates that software can't manage. I've decided to use the Mesa Electronics 5i20 "Anything I/O Card". What I find most attractive about it is that it is "open". The board contains a 200K gate Xilinx FPGA, and an interface to the PCI bus. Seventy-two of the FPGA pins are brought out of the back of the PC on three 50 pin ribbon cables. What you do with those pins is up to you, because the FPGA is reconfigurable. The board comes with several FPGA configurations, such as 4 channel analog servo (4 DACs, 4 encoder counters, and misc I/O). Most users just load one of those configurations into the part and use it. (EMC2 already has a driver for the 4 channel servo configuration.) However, I'm going to be using stepper motors, not servos, so I'll have to modify the FPGA design. Linux hosted development tools for the FPGA are available free from Xilinx, and I already know in general terms how to make a hardware step pulse generator. The resulting FPGA configuration and the EMC2 HAL driver for it will of course be released under the GPL as part of the EMC project. Several other EMC people are interested in the 5i20, and we're working on a group buy to get the already quite reasonable $199 price down to the five-piece price of $159. Interested? Contact me! So, are 72 pins of I/O enough? To do that I've put together a list of everything that I might someday want to connect to the PC:
(posted: 09 Dec 2006 16:05) (permalink) |
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